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Amandeep Kaur

Assistant Professor

Electrical Engineering

IIT Jodhpur

Biography

I am an Assistant Professor in the department of Electrical Engineering, Indian Institute of Technology Jodhpur. My research is focussed on analog and mixed signal integrated circuit design which is generic as well as application specific like CMOS image sensors and biomedical circuits and systems.

I received my doctoral degree in the department of Electrical Engineering from Indian Institute of Technology Delhi, 2019. During my Ph.D., I have designed and characterized various integrated circuits like comparators, LDO, single stage ADC, two stage ADC, hybrid ADC, and two complete camera systems for high speed and low power applications. The work is published in elite transactions and conferences.

If anyone is interested in the area of analog and mixed signal VLSI design, then feel free to contact me.

Interests

  • Analog/Mixed Signal IC Design
  • Data Converters (ADC, DAC)
  • Interfacing Circuits/Readout Electronics
  • Biomedical Circuits and Systems
  • CMOS Image Sensors

Education

  • PhD in Electrical Engineering, 2019

    IIT Delhi

  • M.Tech in VLSI Design, 2012

    Thapar University

  • B.Tech in ECE, 2010

    Kurukshetra University

Recent and Upcoming

  • May 2020: Our paper on “On-array compressive acquisition in CMOS image sensors using accumulated spatial gradients” has been accepted in IEEE Transactions on Circuits and Systems for Video Technology.
  • January 2020: Our paper on, “A CMOS Image Sensor with column-Parallel cyclic-SAR ADC” has been accepted in IEEE International Symposium on Circuits and Systems (ISCAS is the flagship conference of circuits and systems society).
  • November 2019: Organised a 2-days Workshop on “Analog and Digital Circuit Design using Cadence EDA tool” at IIT Jodhpur.
  • October 2019: Our work on “A reconfigurable cyclic ADC for biomedical applications”, has been presented in IEEE Biomedical Circuits and Systems Conference, Japan, 2019.
  • June 2019: Our work on “A power efficient image sensor readout with on-chip delta-interpolation using reconfigurable ADC”, has been published in IEEE Sensors Journal, 2019.

Research

High frame rate CMOS image sensor: A CMOS image sensor with column-parallel cyclic ADC is designed and fabricated in AMS 350 nm CMOS process. All the associated circuits including pixel array, ADC, vertical scanners, reference generation, clock circuitry etc are integrated on the same integrated circuit. The camera results in a frame rate of 1300 fps. The layout and the raw images captured from the designed camera are shown.

Layout of high frame rate CMOS image sensor
Raw images captured from my own designed high speed camera

A power efficient CMOS image sensor: The CMOS image sensor with column-parallel hybrid ADC is designed and fabricated in AMS 350 nm CMOS process.

Layout of low power CMOS image sensor
Raw images captured from my own designed power efficient camera

A two-stage cyclic ADC: The two-stage cyclic ADC with a 2.5-bit/phase architecture is designed and fabricated in UMC 180 nm CMOS process. The pipelined operation of the two stages along with the relaxed design constraints of the second stage resulted in a competitive performance as compared to the state-of-the-art. The microchip photograph and the measured non linearities are shown.

Microchip photograph of two-stage cyclic ADC
Measured DNL and INL

A single stage cyclic ADC: An area efficient and low power single stage cyclic ADC using 2.5-bits in 1.5-bit framework is designed and fabricated in UMC 180 nm CMOS technology. In natural images, the neighbouring pixels contain almost similar information. Instead of reading the entire pixel values, only the difference between the pixels is read. The ADC resolves the delta difference, which reduces the number of clock cycles and hence the readout power. These ADCs are also preferred for biomedical applications.

Microchip photograph of single-stage cyclic ADC
Measured DNL and INL
Measurement results
Low latency and low power comparator: An adaptive sampling based low latency and a low power comparator is designed and fabricated in UMC 180 nm CMOS process. Circuit consumes total power of 4.289 microW while operating at the clock frequency of 20 MHz. Measurement results shows the reduction in comparator latency by 75% compared to the state of the art comparators.
Measurement results and Microchip photograph of comparator

Experience

 
 
 
 
 

Assistant Professor

Indian Institute of Technology Jodhpur

Sep 2019 – Present Jodhpur
 
 
 
 
 

Young Faculty Associate

Indian Institute of Technology Jodhpur

May 2019 – Sep 2019 Jodhpur
 
 
 
 
 

Assistant Professor

Sharda University

Jul 2012 – Jul 2013 Greater Noida

Professional Activities

  • Reviewer of IEEE TCAS - II, IEEE TVLSI, IEEE TCSVT, IEEE Sensors Journal.
  • Reviewer of IEEE ISCAS conference.

Academic Activities

  • Department Faculty Board (DFB) Convener.
  • Member Ph.D. Admission Committee.
  • Member M.Tech Admission Committee.

Awards and Honors

Awards

  • Best among top 5% papers in IEEE Sensors, 2018.

  • Best paper award in IEEE ISOCC, 2017.

Honors

  • Gold medal in B.Tech, 2010.

Teaching

Courses

EEL7060 (July 2019 - Nov 2019): Analog and Interfacing Circuits

EEL7440 (Jan 2020 - ): Image Sensor Design and Applications

CSL7333 (Jan 2020 - ): Neuromorphic Hardware Implementation

Labs

EEP7030 (July 2019 - Nov 2019): Sensors and IoT Lab

EEP7110 (Jan 2020 -): Integrated Circuit Design Lab

Contact

  • 0291 280 1368
  • Room no - 220, First Floor, Electrical Engineering Department, IIT Jodhpur, 342037