I am an Assistant Professor in the department of Electrical Engineering, Indian Institute of Technology Jodhpur. My research is focussed on analog and mixed signal integrated circuit design which is generic as well as application specific like CMOS image sensors and biomedical circuits and systems.
I received my doctoral degree in the department of Electrical Engineering from Indian Institute of Technology Delhi, 2019. During my Ph.D., I have designed and characterized various integrated circuits like comparators, LDO, single stage ADC, two stage ADC, hybrid ADC, and two complete camera systems for high speed and low power applications. The work is published in elite transactions and conferences.
If anyone is interested in the area of analog and mixed signal VLSI design, then feel free to contact me.
PhD in Electrical Engineering, 2019
M.Tech in VLSI Design, 2012
B.Tech in ECE, 2010
High frame rate CMOS image sensor: A CMOS image sensor with column-parallel cyclic ADC is designed and fabricated in AMS 350 nm CMOS process. All the associated circuits including pixel array, ADC, vertical scanners, reference generation, clock circuitry etc are integrated on the same integrated circuit. The camera results in a frame rate of 1300 fps. The layout and the raw images captured from the designed camera are shown.
A power efficient CMOS image sensor: The CMOS image sensor with column-parallel hybrid ADC is designed and fabricated in AMS 350 nm CMOS process.
A two-stage cyclic ADC: The two-stage cyclic ADC with a 2.5-bit/phase architecture is designed and fabricated in UMC 180 nm CMOS process. The pipelined operation of the two stages along with the relaxed design constraints of the second stage resulted in a competitive performance as compared to the state-of-the-art. The microchip photograph and the measured non linearities are shown.
A single stage cyclic ADC: An area efficient and low power single stage cyclic ADC using 2.5-bits in 1.5-bit framework is designed and fabricated in UMC 180 nm CMOS technology. In natural images, the neighbouring pixels contain almost similar information. Instead of reading the entire pixel values, only the difference between the pixels is read. The ADC resolves the delta difference, which reduces the number of clock cycles and hence the readout power. These ADCs are also preferred for biomedical applications. Low latency and low power comparator: An adaptive sampling based low latency and a low power comparator is designed and fabricated in UMC 180 nm CMOS process. Circuit consumes total power of 4.289 microW while operating at the clock frequency of 20 MHz. Measurement results shows the reduction in comparator latency by 75% compared to the state of the art comparators.
Best among top 5% papers in IEEE Sensors, 2018.
Best paper award in IEEE ISOCC, 2017.
EEL7060 (July 2019 - Nov 2019): Analog and Interfacing Circuits
EEL7440 (Jan 2020 - ): Image Sensor Design and Applications
CSL7333 (Jan 2020 - ): Neuromorphic Hardware Implementation
EEP7030 (July 2019 - Nov 2019): Sensors and IoT Lab
EEP7110 (Jan 2020 -): Integrated Circuit Design Lab