Dr. Palash Das

Assistant Professor, Department of Computer Science, IIT Jodhpur, Rajasthan, India. I am looking for motivated students to join at various levels like masters/Ph.D.

Dr. Palash Das has received his B.Tech. Degree in CSE from the West Bengal University of Technology and an M.E. degree in CSE from the Indian Institute of Engineering Science and Technology, Shibpur. He completed his Ph.D. from IIT Guwahati in April 2022. Presently, he is working as an Assistant Professor in the department of CSE, IIT Jodhpur. His research interests include Near-Memory Processing, Hardware Designing, and AI/ML accelerators under the broad domain of Computer Architecture. He has also worked as an Assistant Professor in the department of CSE at Dumkal Institute of Engineering and Technology and received a Certificate of Appreciation for Quality Teaching and Academic Performance. He is the recipient of the National Scholarships Merit Certificate for secondary examination and also received the prestigious Intel Fellowship 2020. He has published multiple research papers in popular Journals and Conferences like IEEE Transaction on Computers (TC), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), ACM Journal on Emerging Technologies in Computing Systems (JETC), Design, Automation and Test in Europe (DATE), ACM Great Lakes Symposium on VLSI (GLSVLSI), and IEEE International Conference on Very Large Scale Integration (VLSI-SoC). He has received travel grants from ACM India-IARCS, DAC 2022, and VLSID 2018.

Journals

  1. Atul Kumar, Dipika Deb, Shirshendu Das, and Palash Das. "edAttack: Hardware Trojan Attack on On-Chip Packet Compression." IEEE Design and Test journal, 2023 (Accepted through NOCS).
  2. Palash Das, Shashank Sharma, and Hemangee K. Kapoor. "ALAMNI: Adaptive LookAside Memory based Near-Memory Inference Engine for Eliminating Multiplications in Real-Time."IEEE Transactions on Computers (TC), 2022.
  3. Palash Das and Hemangee K. Kapoor. "nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.
  4. Palash Das, and Hemangee K. Kapoor. "CLU: A near-memory accelerator exploiting the parallelism in Convolutional Neural Networks". ACM Journal on Emerging Technologies in Computing Systems (JETC), ACM, 2020.
  5. Bikromadittya Mondal, Palash Das, Pradyut Sarkar, and Susanta Chakraborty, “A Comprehensive Fault Diagnosis Technique for Reversible Logic Circuit”, Computers and Electrical Engineering, ELSEVIER DOI: 10.1016/j.compeleceng. 2014.08.003, 2014.
  6. Palash Das, Bikromadittya Mondal (2013), “Extended K-Map for Minimizing Multiple Output Logic Circuits”, International Journal of VLSI Design & Communication Systems(VLSICS), Vol. 4, No.4, August 2013.

Conferences

  1. P. Das and H. K. Kapoor "NDIE: A Near DRAM Inference Engine Exploiting DIMM's Parallelism." Asia Pacific Conference On Circuits And Systems (APCCAS) 2023, IEEE.
  2. A. Kumar, D. Deb, S. Das, and P. Das, "edAttack: Hardware Trojan Attack on On-Chip Packet Compression." International Symposium on Networks-on-Chip (NOCS) 2023, in association with IEEE Design and Test journal.
  3. P. Das, A. Joshi, and H. K. Kapoor "Hydra: A near hybrid memory accelerator for CNN inference" Design, Automation and Test in Europe Conference | The European Event for Electronic System Design & Test, ACM, DATE, 2022.
  4. I. Longchar, P. Das, and H. K. Kapoor “ZaLoBI: Zero avoiding Load Balanced Inference accelerator.”, 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, 2022.
  5. C.Joshi, P.Das, A. Kulkarni, and H. K. Kapoor "Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors" The 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM.
  6. P. Das and H. K. Kapoor "Towards Near Data Processing of Compare Operations in 3D-stacked memory" The 28th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2018, ACM.
  7. P. Das, S. Lakhotia, P. Shetty, and H. K. Kapoor "Towards Near Data Processing of Convolutional Neural Networks" 31st International Conference on VLSI Design (VLSID) 2018, IEEE.
  8. P. Das, B. Mondal, “Signature Analysis for Synthesis of Reversible Circuits”, 18th IEEE International Symposium on VLSI Design (VDAT) 2014, IEEE.

Others

  1. Palash Das and Hemangee K. Kapoor. "CLU: A near-memory accelerator exploiting the parallelism in Convolutional Neural Networks". 15th Academic Research and Careers for Students Symposium (ARCS 2021).
  2. Ph.D. Forum: Palash Das and Hemangee K. Kapoor. "Accelerating CNN inference near to the memory by exploiting parallelism, sparsity, and redundancy". Design, Automation and Test in Europe Conference | The European Event for Electronic System Design & Test, ACM, DATE 2022.
  3. Ph.D. Forum: Palash Das and Hemangee K. Kapoor. "Near-Memory Architectures for CNNs while Exploiting Parallelism, Sparsity, and Redundancy". Design Automation Conference (DAC), 2022. (accepted)

Experience

Assistant Professor

Department of CSE, IIT Jodhpur

I am an instructor of undergraduate (UG) and postgraduate (PG) courses. I am also involved in research under the broad domain of Computer Architecture.

August 2022 - Till Date

Research Scholar and Teaching Assistant

Department of CSE, IIT Guwahati, India
  • Parallel Computer Architecture(CS527: UG+PG)
  • Introduction to VLSI Design, Verification and Test (CS524: UG+PG)
  • Computer Organisation and Architecture (CS222: UG)
  • Digital Design(CS221: UG)
  • Introduction to Computing(CS101: UG)
  • Hardware Laboratory(CS223: UG)
  • Digital Design(CS221: UG)
July 2015 - April 2022

Assistant Professor

Department of CSE, Dumkal Institute of Engg. & Tech, W.B.U.T., India

During this period, I was the instructor of several undergraduate (UG) courses like introduction to programming, object-oriented technology (C++, Java), and operating systems. I have guided several UG final year projects as well. I have been awarded the "Certificate of Appreciation for Quality teaching and Academic performance" by the institute. I feel glad to see my students contribute generously to their respective fields in various reputed industries and academia.

August 2009 - June 2015

Education

Indian Institute of Technology (I.I.T), Guwahati

Doctor of Philosophy (Ph.D.)
Computer Science & Engineering (C.S.E)
July 2015 - April 2022

Indian Institute of Engineering Science and Technology, Shibpur (I.I.E.S.T, Formerly known as B.E.S.U)

Master of Engineering (M.E.)
Computer Science & Engineering (C.S.E)
May 2011 - April 2013

West Bengal University of Technology (W.B.U.T)

Bachalor of Technology (B.Tech)
Computer Science & Engineering (C.S.E)
September 2005 - August 2009

Skills

Programming Languages
Tools and Simulators

Teaching

Honors, Achievements, & Fellowships

Professional Services and Memberships


  • Program Committee Member of "Data Science - Scalable Algorithms and Analytics" Track of International Conference on High Performance Computing, Data, and Analytics (HiPC), 2023.

  • Reviewer of IEEE Transactions on Parallel and Distributed Systems (TPDS), December 2021.

  • Resource Person in the workshop under the strengthening component of DBT-STAR College Scheme, Ministry of Science and Technology, GOI, 2021.

  • Talk on Near-memory processing in TEQIP-III sponsored short term course on Advanced Computer Architecture, Department of CSE, IIT Guwahati, 2018.

  • Member, IEEE.

  • Member, ACM.
Girl in a jacketOffice

Room No 308, Department of CSE, IIT Jodhpur,
N.H. 62, Nagaur Road, Karwar,
Pin 342030, Office Number (91 291) 280 1256,
Email palashdas[at]iitj[dot]ac[dot]in

Girl in a jacketResidence Address

Papia Villa, Birnagar,
Mahamayasthan, Raiganj, Uttar Dinajpur,
West Bengal, India, Pin 733134.

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