INSPIRE Faculty, Senior
Scientific Officer
Artificial Intelligence of
Things Fab Lab (AIOT)
Indian Institute of
Technology Jodhpur
pragya@iitj.ac.in
Sponsored Projects
Sub-5nm
Semiconductor Device Investigation and Compact Model Development, funded by
INSPIRE Research Grant from Department of Science and Technology, Govt. of
India (ongoing)
Running Projects
Establishment of Class 100
clean room facility for AIOT Fab lab, funded by RISL, JCKIF and IIT Jodhpur (ongoing)
2022: Invited speaker from
Women in Electron Device Society (WiEDS) in IEEE ICEE
Conference 2022 at
Bangalore, India
2021: IEEE Senior Member
2020: IEEE EDS compact
modeling committee technical member
2020: Selected for
prestigious Ramanujan fellowship 2020 by SERB, Department of Science
and Technology, India
2019: Awarded INSPIRE
faculty fellowship 2019 by INSPIRE, Department of Science and
Technology, India
2019: First Indian Women
Recipient of IEEE EDS Early
Career Award 2019
2018: Appeared in IEEE
Electron Device Society golden list of reviewers.
2018: Invited Speaker in
Workshop on Compact Modeling, Anaheim, USA.
2017: Research work is
highlighted by IEEE Women in Engineering Society.
2015: Travel grant from
Department of Science and Technology (DST) for IEEE DRC conference.
2014: Best paper award in
IEEE India conference (INDICON), Pune, India, Dec.
2014.
2013: Best paper award in
IEEE Prime Asia Conference, Visakhapatnam, Dec. 2013.
2011: Gold medal for
academic excellence in M.tech
Microelectronics at Panjab University,
Chandigarh, India.
2010: Best Student Award in IEEE
ICAER'10 conference, U.I.E.T
Chandigarh, India.
"Industry Standard FDSOI
Compact Model BSIM-IMG for IC Design", Link
[1]
P. Kushwaha et.al., "Impact of BB84 QKD Transmitter's Parameter Mismatch on Secure Key
Generation Rate", Photonic Network Communications Journal, https://doi.org/10.1007/s11107-023-01010-3,
Feb 2024 (Link).
[2]
M. S. Nazir, A. Pampori, R. Dangi, P. Kushwaha, E. Yadav, S. Sinha, and Y.
S. Chauhan, "Characterization and Modeling of Drain Lag using a Modified
RC Network in the ASM-HEMT Framework", Solid
State Electronics, Vol. 199, art. no. 108490, January 2023.
[3]
M. S. Nazir, P. Kushwaha, A.
Pampori, S. A. Ahsan, and Y. S. Chauhan,
"Electrical Characterization and Modeling of GaN
HEMTs at Cryogenic Temperatures", IEEE
Transactions on Electron Devices, Vol. 69, Issue 11, November 2022.
[4]
Girish Pahwa, Pragya
Kushwaha, Avirup Dasgupta, Sayeef Salahuddin, and Chenming Hu, "Compact Modeling of Temperature Effects
in FDSOI and FinFET Devices
Down to Cryogenic Temperatures", IEEE Transactions on Electron Devices,
Accepted July 2021.
[5]
P. Kushwaha, A. Dasgupta,
M.-Y. Kao, H. Agarwal, S. Salahuddin, C. Hu, "Design Optimization
Techniques in Nanosheet Transistor for RF Applications", IEEE Transactions
on Electron Devices, Vol. 67, Issue 10, 2020.
[6]
Dasgupta, S. S. Parihar, H.
Agarwal, P. Kushwaha, Y. S. Chauhan and C. Hu, "Compact Model for Geometry
Dependent Mobility in Nanosheet FETs", IEEE Electron Device Letters, 2020.
[7]
A. Dasgupta, S. S. Parihar,
P. Kushwaha, H. Agarwal, M.-Y. Kao, S. Salahuddin, Y. S. Chauhan and C. Hu,
"BSIM Compact Model for Quantum Confinement in
Advanced Nanosheet FETs", IEEE Transactions on Electron Devices (Early
access), 2020.
[8]
P. Kushwaha, H. Agarwal, Y.
Lin, A. Dasgupta, M. Kao, Y. Lu, Y. Yue, X. Chen, J. Wang, W. Sy, F. Yang, P.
C. Chidambaram, S. Salahuddin, C. Hu, “Characterization and Modeling of Flicker
Noise in FinFETs at Advanced Technology node”, in
IEEE Electron Device Letters, vol 40, no 6, pp. 985-988, doi
10.1109/LED.2019.2911614, ISSN 0741-3106, June, 2019.
[9]
H. Agarwal, C. Gupta, R.
Goel, P. Kushwaha, Y.-Kai Lin, M.-Yen Kao, J. P. Duarte, H.-Lin Chang, Y. S.
Chauhan, S. Salahuddin, and C. Hu, “BSIM-HV: High
Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect”,
accepted in IEEE Transactions on Electron Devices, June 2019.
[10]Y-Kai Lin, H. Agarwal, M-Yen Kao, J. Zhou, Y.-Hung Liao, A.
Dasgupta, P. Kushwaha, S. Salahuddin, and C. Hu, “Spacer Engineering in
Negative Capacitance FinFETs” in IEEE Electron Device
Letters, vol. 40, no. 6, pp. 1009-1012, doi: 10.1109/LED.2019.2911104, June 2019.
[11]M.-Yen Kao, Y.-Kai Lin, H. Agarwal, Y.-Hung Liao, P. Kushwaha, A.
Dasgupta, S. Salahuddin, and C. Hu, “Optimization of NCFET
by Matching Dielectric and Ferroelectric Non-uniformly along the Channel” in
IEEE Electron Device Letters, vol. 40, no. 5, pp. 822-825, May 2019. doi: 10.1109/LED.2019.2906314
[12]Y.-Kai Lin, H. Agarwal, P. Kushwaha, M.-Yen Kao, Y.-Hung Liao, S.
Salahuddin, and C. Hu, “Analysis and Modeling of Inner Fringing Field Effect on
Negative Capacitance FinFETs” in IEEE Trans. on
Electron Devices, vol. 66, no. 4, pp. 2023-2027, doi:
10.1109/TED.2019.2899810, April 2019.
[13]H. Agarwal, P. Kushwaha, Y.-Kai Lin, M.-Yen Kao, Y.-Hung Liao, A.
Dasgupta, S. Salahuddin, and C. Hu, “Proposal for Capacitance Matching in
Negative Capacitance Field Effect Transistors,” in IEEE Electron Device
Letters, vol. 40, no. 3, pp. 463-466, doi: 10.1109/LED.2019.2891540, March 2019.
[14]D. Rajasekharan, P. Kushwaha, S. S.
Chauhan, and Y. S. Chauhan, “Non-Boolean Associative Processing using FDSOI MOSFET-based Inverter,” in IEEE Transactions on
Nanotechnology, 2018 (Link)
[15]M.-Y. Kao, A. Sachid, Y.-K. Lin, Yu-H.
Liao, H. Agarwal, P. Kushwaha, J. P. Duarte, H.-L. Chang, S. Salahuddin and C.
Hu, “Variation Caused by Spatial Distribution of Dielectric and Ferroelectric
Grains in a Negative Capacitance Field-Effect Transistor ”
accepted in IEEE Transactions on Electron Devices, 2018.
[16]H. Agarwal, P. Kushwaha, Y.-K. Lin, M.-Y. Kao, Yu-H. Liao, J. P.
Duarte, S. Salahuddin, and C. Hu, “NCFET Design
Considering Maximum Interface Electric Field,” in IEEE Electron Device Letters,
2018. (Link)
[17]P. Kushwaha, H. Agarwal, Y.-K. Lin, M.-Y. Kao, J. P. Duarte, H.-L.
Chang, W. Wong, X. J. Fan, Y. S. Chauhan, S. Salahuddin, and C. Hu, Modeling of
Advanced RF Bulk FinFETs, IEEE Electron Device
Letters, vol. 39, no. 6, pp. 791 to 794, doi:10.1109/LED.2018.2825422, 2018.(Link)
[18]H. Agarwal, P. Kushwaha, J. P. Duarte, Y.-K. Lin, A. Sachid, M.-Y. Kao, H.-L. Chang, S. Salahuddin and C. Hu,
“Engineering Negative Differential Resistance in NCFETs
for Analog Applications”
IEEE Transactions on Electron Devices, 2018. (Link)
[19]H. Agarwal, P. Kushwaha, J. P. Duarte, Y.-K. Lin, A. Sachid, M.-Y. Kao, H.-L. Chang, S. Salahuddin and C. Hu,
"Designing 0.5V 5nm HP
and 0.23V 5nm LP NC-FinFETs with Improved Ioff
Sensitivity in Presence of Parasitic Capacitance," IEEE Trans. Electron
Devices, 2018. (Link)
[20]A. K. Dabhi, A. Dasgupta, P. Kushwaha, H. Agarwal, C. Hu, and Y. S.
Chauhan, "Modeling of Induced Gate Thermal Noise including Back Bias
Effect in FD-SOI MOSFET", IEEE Microwave and Wireless Components Letters,
2018. (Accepted)
[21]Yen-Kai Lin, Pragya Kushwaha, Juan Pablo Duarte, Huan-Lin Chang,
Harshit Agarwal, Sourabh Khandelwal, Angada Sachid,
Michael Harter, Josef Watts, Yogesh S. Chauhan, Sayeef
Salahuddin, and Chenming Hu, "New Mobility Model
for Accurate Modeling of Transconductance in FDSOI
MOSFETs," IEEE Trans. Electron Devices, 2018. [Link]
[22]Yen-Kai Lin, Pragya Kushwaha, Harshit Agarwal, Huan-Lin Chang, Juan
Pablo Duarte, Angada Sachid, Sourabh Khandelwal, Sayeef Salahuddin, and Chenming
Hu, "Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate
Currents in UTBSOI MOSFETs," IEEE Trans.
Electron Devices, vol. 64, no. 10, pp. 3986–3990, Oct. 2017. [Link]
[23]Yen-Kai Lin, Juan Pablo Duarte, Pragya Kushwaha, Harshit Agarwal,
Huan-Lin Chang, Angada Sachid, Sayeef
Salahuddin, and Chenming Hu, "Compact Modeling
Source-to-Drain Tunneling in Sub-10nm GAA FinFET with
Industry Standard Model," IEEE Trans. Electron Devices, vol. 64, no. 9,
pp. 3576–3581, Sep. 2017. [Link]
[24]Y. Sahu, P. Kushwaha, A. Dasgupta, C. Hu, and Y. S. Chauhan,
"Compact Modeling of Drain Current Thermal Noise in FDSOI
MOSFETs Including Back-Bias Effect", in IEEE Transactions on Microwave
Theory and Techniques, vol 65, issue 7, pp. 2261-2270, July 2017.
[25]P. Kushwaha, S. Khandelwal, J. P. Duarte, C. Hu, Y. S. Chauhan,
"RF Modeling of FDSOI Transistors Using Industry
Standard BSIM-IMG Model," in IEEE Transactions
on Microwave Theory and Techniques , vol.PP, no.99, pp.1-7, 2016. link
[26]P. Kushwaha, B. Krishna K, H. Agarwal , S.
Khandelwal, J. P. Duarte, C. Hu, Y. S. Chauhan, “Geometrically Scalable Thermal
Resistance Model for FDSOI Transistors”, Volume 56,
Pages 171-176, Microelectronics Journal, 2016.
[27]P. Kushwaha, A. Dasgupta, Y. Sahu, S. Khandelwal, C. Hu and Y. S. Chauhan , “Characterization of High Frequency Noise of 8 nm
thin FDSOI MOSFET for 1-18 GHz”, in IEEE Journal of
Electron Devices Society, 2016.
[28]A. K. Kompala, P. Kushwaha, H. Agarwal,
S. Khandelwal, J. P. Duarte, C. Hu and Y. S. Chauhan., “Modeling of Nonlinear
Thermal Resistance in FinFETs”, in Japanese Journal
of Applied Physics, 2016.
[29]S. Khandelwal, H. Agarwal, P. Kushwaha, J. P. Duarte, A. Medury, Y. S. Chauhan, S. Salahuddin, and C. Hu,
"Unified Compact Model Covering Drift-Diffusion to Ballistic Carrier
Transport", IEEE
Electron Device Letters, Vol. 37, Issue 2, Feb. 2016
[30]H. Agarwal, P. Kushwaha, C. Gupta, S. Khandelwal, C. Hu, and Y. S.
Chauhan, "Analysis and Modeling of Flicker Noise in Lateral Asymmetric
Channel MOSFETs", Solid State Electronics, Vol. 115, Part A, Jan. 2016.
[31]P. Kushwaha, N. Paydavosi, S. Khandelwal,
C. Yadav, H. Agarwal, J. P. Duarte, C. Hu, Y. S.
Chauhan, “Modeling the Impact of
Substrate Depletion in FDSOI MOSFETs” in Solid State
Electronics, Vol. 104, Issue 2, Feb. 2015.
[32]H. Agarwal, C. Gupta, P. Kushwaha, C. Yadav, J. P. Duarte, S.
Khandelwal, C. Hu, and Y. S. Chauhan, "Analytical Modeling and
Experimental Validation of Threshold Voltage in BSIM6
MOSFET Model", IEEE Journal of Electron Devices Society, Vol. 3, Issue 3,
March 2015.
[33]C. Yadav, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y. S. Chauhan,
and C. Hu, "Modeling of GaN based Normally-off FinFET", IEEE Electron Device Letters, Vol. 35, Issue
6, June 2014.
[1]
Y. Machhiwar,
P. Kushwaha, H. Agarwal, “Optimization of Source/Drain-epi Region Height
in GAA Nanosheet FET for RF Applications”, 2024 IEEE Device Research Conference,
June 2024 (accepted).
[2]
M. H. Ansari, R. Dangi, A. Pampori, P. Kushwaha, E. Yadav, S. Sinha, and Y. S.
Chauhan, "A Width-Scalable SPICE Model of GaN-HEMTs for
X-band RF Applications", IEEE Electron Devices Technology and
Manufacturing Conference (EDTM), Seoul, Korea, Mar.
2023.
[3]
M. S. Nazir, A. Pampori, R. Dangi, P. Kushwaha, E. Yadav, S. Sinha,
and Y. S. Chauhan, "Characterization and Modeling of Drain Lag using a
Modified RC Network in the ASM-HEMT Framework",
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Granada, Spain, September 2022
[4]
R. Dangi, A. Pampori, P. Kushwaha, E. Yadav, S. Sinha, and Y. S.
Chauhan, "A width-scalable SPICE compact model for GaN
HEMTs including self-heating effect", 80th
Device Research Conference (DRC), Ohio, USA, June, 2022.
[5]
Y. S. Chauhan, A. Pampori, R. Dangi, P. Kushwaha, E. Yadav, S. Sinha,
"A Turnkey Large-Signal Model for Amplifier Design in 5G
Spectra using AlGaN/GaN HEMTs",
IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Oita, Japan, Mar. 2022. (Invited)
[6]
Pragya Kushwaha, Santanu Sinha, Chiranjit K Karmakar, Manish Sahu, Rakesh K Kaneriya, Punam Pradeep Kumar, Apurba Bhattacharya,
"Characterization of GaN HEMT
at Cryogenic Temperatures", IEEE MTT-S
International Microwave and RF Conference (IMaRC),
Accepted, October 2021.
[7]
H. Agarwal, P. Kushwaha,
A. Dasgupta, M.-Y. Kao, T. Morshed, G. Workman, K. Shanbhag, X. Li, Y. S.
Chauhan, S. Salahuddin and C. Hu,, "BSIM-IMG: Advanced Model for UTBSOI
Transistors with Back Gate Inversion", IEEE Electron Devices Technology
and Manufacturing Conference (EDTM), Penang,
Malaysia, Mar. 2020.
[8]
P.Kushwaha et.al., "Modeling the Quantum Gate capacitance of
Nano-Sheet Gate-All-Around MOSFET ", IEEE SOI–3D–Subthreshold
Microelectronics Technology Unified Conference (S3S),
San Francisco, USA, Oct. 2019.
[9]
C. K. Dabhi, P. Kushwaha,
H. Agarwal, S. S. Chauhan, C. Hu, and Y. S. Chauhan, “Physical Analysis of
Non-monotonic DIBL Dependence on Back Gate Bias in
Thick Front Gate Oxide FDSOI MOSFETs”, IEEE
SOI–3D–Subthreshold Microelectronics Technology Unified Conference (S3S), San Francisco, USA, Oct. 2019.
[10]
P. Kushwaha, J.P. Duarte, Y-K. Lin, H. Agarwal, H-L. Chang, A. Sachid, S. Salahuddin, Y.S.
Chauhan, C. Hu, “Unified Compact Model for Gate All Around FETs- Nanosheets,
Nanowires, Multi Bridge Channel MOSFETs”, Workshop on Compact Modeling,
Anaheim, CA, USA, 2018. (Link)
[11]P.
Kushwaha, H. Agarwal, C. K. Dabhi,
Y.-K. Lin, J. P. Duarte, C. Hu, and Y. S. Chauhan, "A Unified Flicker
Noise Model for FDSOI MOSFETs Including Back-bias
Effect", IEEE International Conference on Electronics, Computing and
Communication Technologies (CONECCT), Bengaluru,
India, Mar. 2018.
[12]Y.-K.
Lin, M.-Y. Kao, H. Agarwal, Y. -H. Liao, P. Kushwaha, K.
Chatterjee, J. P. Duarte, H.-L. Chang, S. Salahuddin, and C. Hu, “Effect of
Polycrystallinity and Presence of Dielectric Phases on NC-FinFET
Variability“, IEEE International Electron Devices
Meeting (IEDM), San Francisco, CA, USA, Dec 2018
[13]J.
P. Duarte, Y.-K. Lin, Y. -H. Liao, A. Sachid,
M.-Y. Kao, H. Agarwal, P. Kushwaha, K. Chatterjee, D. Kwon, H.-L.
Chang, S. Salahuddin, and C. Hu, “Negative-Capacitance FinFETs:
Numerical Simulation, Compact Modeling and Circuit Evaluation”, IEEE
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sept. 2018 (invited)
[14]M.
Bhoir, P. Kushwaha, Y. S. Chauhan and N. R. Mohapatra, "Impact of
Substrate on the Frequency Behavior of Trans-conductance in Ultra-thin Body and
BOX FDSOI MOS Devices – A Physical Insight",
IEEE International Symposium on VLSI Technology, Systems and Applications
(VLSI-TSA), Hsinchu, Taiwan, Apr. 2017.
[15]R.
Singh, P. Kushwaha, S. Ghosh, B. Parvais, Y.
S. C and A. Dixit, "Characterization and Modeling of N-Channel Bulk FinFETs from DC to High Frequencies", IEEE
International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, Taiwan, Oct. 2017.
[16]P.
Kushwaha, R. Agarwal, H. Agarwal, C.
Gupta, S. Khandelwal, J. P. Duarte, Y. K. Lin, H. L. Chang, C. Hu, and Y. S.
Chauhan, "Modeling of Threshold Voltage for Operating Point using Industry
standard BSIM-IMG Model",
in IEEE EDSSC 2016.
[17]P.
Kushwaha, H. Agarwal, M. Bhoir, N.
R. Mohapatra, S. Khandelwal, J. P. Duarte, Y.-K. Lin, H.-L. Chang, C. Hu and Y.
S. Chauhan, "Predictive Effective Mobility Model for FDSOI
Transistors using Technology Parameters", IEEE Conference on
Electron Devices and Solid-State Circuits (EDSSC),
Hong Kong, Aug. 2016.
[18]H.
Agarwal, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y.-K. Lin, H.-L.
Chang, C. Hu, H. Wu, P. D. Ye and Y. S. Chauhan, "Modeling of GeOI and Validation with Ge-CMOS Inverter Circuit using BSIM-IMG Industry Standard Model", IEEE
Conference on Electron Devices and Solid-State Circuits (EDSSC),
Hong Kong, Aug. 2016.
[19]Juan
Pablo Duarte, S. Khandelwal, Huan-Lin Chang, Yen-Kai Lin, P. Kushwaha,
Y. S. Chauhan, and C. Hu, “Modeling Independent Multi-Gate MOSFET,” 2016
Workshop on Compact Modeling (WCM), Washington, D.C.,
USA, May 2016.
[20]P.
Kushwaha, H. Agarwal, S. Khandelwal,
J. P. Duarte, A. Medury, C. Hu and Y. S. Chauhan,
"BSIM-IMG: Compact Model for RF-SOI MOSFETs", in IEEE Device Research Conference (DRC),
Columbus, USA, June 2015.
[21]P.
Kushwaha, S. Khandelwal, J. P.
Duarte, C. Hu, and Y. S. Chauhan, "Thermal Resistance Scaling with Number
of fins in FinFET", SRC
TECHCON, Austin, USA, September 2015.
[22]P.
Kushwaha, S. Khandelwal, C. Hu and
Y. S. Chauhan, "Recent Updates in Industry Standard BSIM-IMG
Model for FDSOI Transistors", International
Workshop on Physics of Semiconductor Devices (IWPSD),
Bangalore, India, Dec. 2015.
[23]C.
Gupta, H. Agarwal, Akira Ito, S. Ghosh, P. Kushwaha, C. Hu, and Y. S.
Chauhan, "Modeling of Zero-Vth MOSFET with Industry Standard BSIM6 Model”, International Workshop on Physics of
Semiconductor Devices (IWPSD), Bangalore, India, Dec.
2015.
[24]J.
P. Duarte, S. Khandelwal, A. Medury, C. Hu, P.
Kushwaha, H. Agarwal, A. Dasgupta, and Y. S. Chauhan "BSIM-CMG: Standard FinFET Compact
Model for Advanced Circuit Design", IEEE European Solid-State Circuit
Conference (ESSCIRC), Graz, Austria, Sept. 2015.
[25]P.
Kushwaha, C. Yadav, H. Agarwal, J. Srivatsava, S. Khandelwal, J. P. Duarte, S. Khandelwal, Y.
S. Chauhan, C. Hu, “BSIM-IMG with Improved Surface
Potential Calculation” in IEEE INDICON, 2014. (Best
Paper Award)
[26]C.
Yadav, P. Kushwaha, H. Agarwal, Y. S. Chauhan, “Threshold Voltage
Modeling of GaN Based Normally-Off Tri-gate
Transistor” in IEEE INDICON, 2014.
[27]Y.
S. Chauhan, P. Kushwaha, S. Khandelwal, C. Yadav, N. Paydavosi,
J. P. Duarte and C. Hu, "BSIMIMG: COMPACT MODEL
FOR UTBBSOI MOSFETs", Workshop on Compact
Modeling, Washington D.C., USA, June 2014. (Invited)
[28]J.
R. Sahoo, H. Agarwal, C. Yadav, P. Kushwaha, S. Khandewal,
R. Gillon, Y. S. Chauhan, "High Voltage LDMOSFET
Modeling using BSIM6 as Intrinsic-MOS Model",
IEEE PrimeAsia, Visakhapatnam, Dec. 2013.
[29]H.
Agarwal, S. Venugopalan, M. Chalkiadaki, N. Paydavosi, J. P. Duarte, S. Agnihotri, C. Yadav, P.
Kushwaha, Y. S. Chauhan, C. C. Enz, A. Niknejad
and C. Hu, "Recent Enhancements in BSIM6 Bulk
MOSFET Model", IEEE International Conference on Simulation of
Semiconductor Processes and Devices (SISPAD),
Glasgow, Scotland, Sept. 2013.
[30]Y.
S. Chauhan, S. Venugopalan, N. Paydavosi, P.
Kushwaha, S. Jandhyala, J. P. Duarte, S. Agnihotri, C. Yadav, H. Agarwal,
A. Niknejad and C. Hu, "BSIM
Compact MOSFET Models for SPICE Simulation", IEEE International Conference
Mixed Design of Integrated Circuits and Systems (MIXDES),
Gdynia, Poland, June 2013.
2023: Poem selected in SAC
ISRO Home Magazine.
2021: Article selected in
SAC ISRO Home Magazine.